Vertical interconnection may be a challenge in three-dimensional technology. Currently, these vertical electrical interconnections are fabricated in silicon through links or vias, commonly denoted by those skilled in the art as Through Silicon Vias (TSV). The fabrication of these through vias TSV may raise some problems relating notably to their filling (for example, with copper) when a barrier and insulation layer is implemented. In order to reach satisfactory densities of TSVs, their form factor (height/diameter ratio) tends to be increased. This generally leads to the use of thinned semiconductor wafers, typically with a thickness less than 120 microns, which may pose a problem for gripping and stress during fabrication.